1. Field of the Invention
The present invention relates to a sampling receiver, and more particularly to a high speed sampling receiver for sampling data with a small amplitude and latching the same to convert a voltage level of the latched data into an adjusted voltage level to a CMOS circuit.
All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will, hereby, be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
2. Description of the Related Art
Data which have been read out from semiconductor memory devices such as DRAM may have a relatively small amplitude, while data to be inputted into the CMOS circuit should have a relatively high amplitude or a high voltage level. A sampling receiver has been used for sampling the small amplitude data from the semiconductor memory device and latching the same to perform a voltage level conversion to a high voltage level adjusted to the CMOS circuit. In one typical example, the conventional sampling receiver includes a master latch circuit and a slave latch circuit. The master latch circuit further includes a differential input transistor pair for receiving an input of data with a small amplitude, and a latch circuit for latching an output from the differential input transistor pair. The slave latch circuit latches an output from the master latch circuit and outputs a latch signal with an adjusted voltage level to the CMOS circuit.
FIG. 1 is a circuit diagram illustrative of a circuit configuration of one typical conventional sampling receiver. The sampling receiver has the following circuit configuration. A differential input transistor pair comprises two n-channel MOS field effect transistors 41 and 42 having respective gate electrodes which are connected to input terminals 31 and 32 respectively. The input terminal 31 receives an input of small amplitude data IN+, while the input terminal 32 receives another input of small amplitude data IN−. Respective source electrodes of the n-channel MOS field effect transistors 41 and 42 are commonly connected through a current supplying n-channel MOS field effect transistor 40 to a ground line 37. A gate electrode of the n-channel MOS field effect transistor 40 is connected to another input terminal 33 which receives an input of a clock signal CLK. Respective drain electrodes of the n-channel MOS field effect transistors 41 and 42 are connected to source electrodes of n-channel MOS field effect transistors 43 and 44, respectively.
A first CMOS inverter comprises the n-channel MOS field effect transistor 43 and a p-channel MOS field effect transistor 45. A second CMOS inverter comprises the n-channel MOS field effect transistor 44 and a p-channel MOS field effect transistor 46. The first and second CMOS inverters are cross-connected to each other to form a bistable circuit. Namely, an input side of the first CMOS inverter is connected to an output side of the second CMOS inverter, while an output side of the first CMOS inverter is connected to an input side of the second CMOS inverter. Further, source and drain electrodes of the p-channel MOS field effect transistor 45 are respectively connected to source and drain electrodes of a p-channel MOS field effect transistor 47. Source and drain electrodes of the p-channel MOS field effect transistor 46 are respectively connected to source and drain electrodes of a p-channel MOS field effect transistor 48. Gate electrodes of the p-channel MOS field effect transistors 47 and 48 are commonly connected to the input terminal 33 receiving the input of the clock signal “CLK”. The p-channel MOS field effect transistors 47 and 48 are provided for controlling operations of the bistable circuit. Namely, the signal latch operation of the bistable circuit is controlled by the clock signal “CLK”. Respective source electrodes of the p-channel MOS field effect transistors 45, 46, 47 and 48 are commonly connected to a power voltage line 36. Further, an n-channel MOS field effect transistor 49 is connected between the respective drain electrodes of the n-channel MOS field effect transistors 41 and 42. A gate electrode of the n-channel MOS field effect transistor 49 is connected to the power voltage line 36.
The master latch circuit in the sampling receiver comprises the n-channel MOS field effect transistors 40, 41, 42, 43, 44 and 49 and the p-channel MOS field effect transistors 45, 46, 47 and 48. The master latch circuit has two outputs (D, D*). The slave latch circuit in the sampling receiver further comprises a set-reset-flip-flop circuit 50 which has two input terminals “S” and “R” and two output terminals 34 “Q” and 35 “Q*”. The input terminal “S” of the slave latch circuit receives the output “D” from the master latch circuit. The input terminal “R” of the slave latch circuit receives the output “D*” from the master latch circuit.
The p-channel MOS field effect transistor 47 is connected in parallel to the p-channel MOS field effect transistor 45, and the p-channel MOS field effect transistor 48 is connected in parallel to the p-channel MOS field effect transistor 46. Upon release of the latch, the p-channel MOS field effect transistors 47 and 48 turn ON, whereby the two outputs (D, D*) of the master latch circuit become high level “H”.
The gate electrode of the n-channel MOS field effect transistor 49 is connected to the power voltage line 36 for allowing the power voltage VDD always applied to the gate electrode, so that the n-channel MOS field effect transistor 49 always remains in the ON-state, to provide a resistance between the respective source electrodes of the n-channel MOS field effect transistors 43 and 44. After the master latch circuit releases the signals from the latch state, then the voltage levels of the respective source electrodes of the n-channel MOS field effect transistors 43 and 44 becomes equal to each other for preparation for a next latch operation upon receipt of a next input signal.
FIG. 2 is a timing chart explaining operations of the conventional sampling receiver of FIG. 1. When the clock signal “CLK” of the low level “L” is inputted into the input terminal 33, the n-channel MOS field effect transistor 40 turns OFF, while the p-channel MOS field effect transistors 47 and 48 turn ON. The differential input transistor pair receives no current supply from the ground line 37 through the OFF-state n-channel MOS field effect transistor 40, whereby the differential input transistor pair is placed into the inoperable state. Since the p-channel MOS field effect transistors 47 and 48 are placed in the ON-state, the two outputs (D, D*) of the master latch circuit are in the high level “H”. Accordingly, the set-reset-flip-flop circuit 50 as the slave latch circuit shows no change of the outputs (Q, Q*).
In the above-described state, if the clock signal “CLK” inputted into the input terminal 33 shows a level-transition from the low level “L” into the high level “H”, then the n-channel MOS field effect transistor 40 turns ON, while the p-channel MOS field effect transistors 47 and 48 turn OFF, whereby the differential input transistor pair and the bistable circuit of the master latch circuit are placed in the operable state, so that the master latch circuit shows the sampling operations for sampling the input signals. At this time, the small amplitude data (IN+) of the high level and the small amplitude data (IN−) of the low level are respectively inputted into the two input terminals 31 and 32 of the differential input transistor pair, whereby the n-channel MOS field effect transistor 41 shows a current increase and a drain voltage drop, while the n-channel MOS field effect transistor 42 shows a current decrease and a drain voltage rise.
The n-channel MOS field effect transistor 43 connected in series to the n-channel MOS field effect transistor 41 shows a transition to the ON-state, while the n-channel MOS field effect transistor 44 connected in series to the n-channel MOS field effect transistor 42 shows a transition to the OFF-state. The bistable circuit, which comprises the n-channel MOS field effect transistors 43 and 44 and the p-channel MOS field effect transistors 45 and 46, shows a positive feed-back operation which causes that the n-channel MOS field effect transistor 43 and the p-channel MOS field effect transistor 46 turn ON, while the n-channel MOS field effect transistor 44 and the p-channel MOS field effect transistor 45 turn OFF. The output (D) of the master latch circuit remains in the high level “H”, while the output (D*) of the master latch circuit becomes low level “L”. This voltage fall of the output (D*) resets the set-reset-flip-flop circuit 50. Accordingly, the output “Q” from the set-reset-flip-flop circuit 50 is latched at the low level “L”, while the output “Q*” is latched at the high level “H”.
Thereafter, when the transition into the low level “L” of the clock signal “CLK” appears, then the n-channel MOS field effect transistor 40 turns OFF, while the p-channel MOS field effect transistors 47 and 48 turn ON. The differential input transistor pair receives no current supply from the ground line 37 through the OFF-state n-channel MOS field effect transistor 40, whereby the differential input transistor pair is placed into the inoperable state. Since the p-channel MOS field effect transistors 47 and 48 are placed in the ON-state, the two outputs (D, D*) of the master latch circuit are placed in the high level “H”. Accordingly, the set-reset-flip-flop circuit 50 as the slave latch circuit shows no change of the outputs (Q, Q*) or holds the latched low level “L” of the output “Q” and the latched high level “H” of the output “Q*”.
If the clock signal “CLK” inputted into the input terminal 33 shows the level-transition from the low level “L” into the high level “H”, then the n-channel MOS field effect transistor 40 turns ON, while the p-channel MOS field effect transistors 47 and 48 turn OFF, whereby the differential input transistor pair and the bistable circuit of the master latch circuit are placed in the operable state, so that the master latch circuit shows the sampling operations for sampling the input signals. At this time, the small amplitude data (IN+) of the low level and the small amplitude data (IN−) of the high level are respectively inputted into the two input terminals 31 and 32 of the differential input transistor pair, whereby the n-channel MOS field effect transistor 42 shows a current increase and a drain voltage drop, while the n-channel MOS field effect transistor 41 shows a current decrease and a drain voltage rise.
The n-channel MOS field effect transistor 44 connected in series to the n-channel MOS field effect transistor 43 shows a transition to the ON-state, while the n-channel MOS field effect transistor 43 connected in series to the n-channel MOS field effect transistor 41 shows a transition to the OFF-state. The p-channel MOS field effect transistor 45 turns ON, while the n-channel MOS field effect transistor 46 turns OFF. The output (D*) of the master latch circuit remains in the high level “H”, while the output (D*) of the master latch circuit becomes low level “L”. This voltage fall of the output (D*) sets the set-reset-flip-flop circuit 50. Accordingly, the output “Q*” from the set-reset-flip-flop circuit 50 is latched at the high level “H”, while the output “Q” is latched at the low level “L”.
Thereafter, when the transition into the low level “L” of the clock signal “CLK” appears, then the n-channel MOS field effect transistor 40 turns OFF, while the p-channel MOS field effect transistors 47 and 48 turn ON. The differential input transistor pair and the bistable circuit are placed into the inoperable state. The two outputs (D, D*) of the master latch circuit are placed in the high level “H”. Accordingly, the set-reset-flip-flop circuit 50 as the slave latch circuit shows no change of the outputs (Q, Q*) or holds the latched low level “L” of the output “Q” and the latched high level “H” of the output “Q”.
The present voltage levels of the small amplitude data (IN+, IN−) are converted to the CMOS levels and latched at those levels even when the transition into the high level “H” of the clock signal “CLK” appears.
As described above, the conventional sampling receiver includes the master latch circuit and the slave latch circuit. The master latch circuit includes the bistable circuit. The bistable circuit comprises the two CMOS inverters, wherein one comprises the n-channel MOS field effect transistor 43 and the p-channel MOS field effect transistor 45, and another comprises the n-channel MOS field effect transistor 44 and the p-channel MOS field effect transistor 46. The two CMOS inverters are connected in series to the differential input transistor pair and the current supplying transistor. If the CMOS inverters are connected directly between the power voltage line and the ground line, a significant transitional through-current appears in the data sampling process. The above series connection may, however, reduce the transitional through-current in the data sampling process, thereby reducing an unnecessary power consumption.
In the above-described conventional circuit configuration, the n-channel MOS field effect transistor 43 included in the CMOS inverter included in the master latch circuit is connected in series to the n-channel MOS field effect transistor 41 included in the differential input transistor pair. Also, the n-channel MOS field effect transistor 44 included in the CMOS inverter included in the master latch circuit is connected in series to the n-channel MOS field effect transistor 42 included in the differential input transistor pair. The externally inputted small amplitude data (IN+, IN−) are sampled upon the high level “H” of the clock signal “CLK”, and then level-converted to the CMOS level by the master latch circuit for supplying output signals (D and D*) to the slave latch circuit 50. An output impedance of the output terminal 34 or 35, on which the falling output signal (D or D*) appears, is given by the sum of source-drain impedances of either a three-stage-series-connection of the n-channel MOS field effect transistors 40, 42 and 44 or another three-stage-series-connection of the n-channel MOS field effect transistors 40, 41 and 43. This means that the output impedance of the falling output signal (D or D*) is thus relatively large.
The relatively large output impedance of the falling output signal (D or D*) causes a relatively large time constant of the falling output signal from the master latch circuit. The relatively large time constant of the falling output signal makes the transistor driving ability small apparently. Namely, the relatively large time constant of the falling output signal increases a delay time in falling of the output signal from the master latch circuit. The increase in the delay time of falling of the output signal from the master latch circuit causes an increase in delay time of latch-operation of the slave latch circuit which comprises the set-reset-flip-flop circuit 50.
In the meantime, recently, the clock signal frequency for the sampling process is often high in accordance with the requirement for high speed signal processings. This makes it necessary to improve the high speed performance in the signal latch operation of the sampling receiver circuit.
In the above circumstances, the clock signal frequency is high, while the delay time of latch-operation of the slave latch circuit is large, for which reason, it is possible, in case, that the delay time in falling of the output signal from the master latch circuit is so large that the clock signal has already been inverted, even the time-delayed latch operation of the slave latch circuit has not yet been completed. In this case, an erroneous latch output signal may appear because the normal latch operation is no longer ensured.
In the above circumstances, the development of a novel high speed sampling receiver free from the above problems is desirable.